1. Field of the Invention
The present invention relates to a signal transmission technology for transmitting signals at high speed between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or machines, and more particularly, to a receiver, hybrid circuit, driver circuit, and signal transmission system for bidirectional signal transmission for carrying out such signal transmission in both directions simultaneously.
2. Description of the Related Art
In recent years, the performance of components used to construct computers and other information processing apparatuses has improved greatly; indeed, dramatic performance improvements have been made, for example, for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and processors and the like. The improvements in the performance of semiconductor memory devices, processors, and the like have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased. Stated more specifically, the speed of signal transmission between a main storage device such as a DRAM and a processor (i.e., between LSIs), for example, is becoming a bottleneck impeding performance improvement for a computer as a whole.
The need for the improvement of signal transmission speed is increasing not only for signal transmission between machines or boards (printed wiring boards), such as between a server and a main storage device or between servers connected via a network, but also for signal transmission between chips or between devices or circuit blocks within a chip because of increasing integration and increasing size of semiconductor chips, decreasing supply voltage levels (low-voltage-swing signals), etc. It is therefore desired to provide a receiver and hybrid circuit (hybrid) for bidirectional signal transmission, capable of achieving high-speed transmission. It is also desired to provide a driver circuit having a linear output impedance suitable for bidirectional transmission or multilevel transmission that can increase the efficiency of use of a signal transmission line or can reduce the number of signal lines without decreasing the signal transmission speed, and a signal transmission system using such a driver circuit.
In order to address the increase in the amount of data transmission between LSIs or between boards or machines, signal transmission speed per pin must be increased. This is to avoid an increase in package cost, etc. due to increased pin count. As a result, inter-LSI signal transmission rates exceeding 1 Gbps, for example, have been achieved in recent years, and in the future (three to eight years from now) signal transmission rates are expected to reach extremely high values (achieving very high signal transmission rates) such as 4 Gbps or even 10 Gbps.
At such high signal frequencies, however, loss occurs in the high signal frequencies due to the skin effect of a signal transmission line, which, coupled with such factors as high-frequency component reflections due to the effects of parasitic inductance and parasitic capacitance, limits the bandwidth of the transmission line. Such limitations may be alleviated, for example, by using large-core cables, but in applications where a large number of signal lines need to be bundled in parallel for large-capacity data transmission, there is a limit to increasing the diameter of the cable bundle. In this way, as the signal transmission frequency increases, there occurs a situation where the signal transmission line itself becomes a bottleneck in signal transmission.
To eliminate such a bottleneck, various techniques are employed, such as bidirectional transmission that transmits signals in both directions simultaneously and multilevel transmission that transmits a large number of bits using one symbol. In bidirectional transmission, a hybrid circuit is used that has the function of separating the net signal voltage for output by subtracting it from the signal voltage of the signal line the signal being sent out by the driver of the hybrid circuit.
Further, in high-speed signal transmission, it is practiced to terminate a signal line in the characteristic impedance of the transmission line (impedance matching) because non-matched line termination would cause signal reflections resulting in the disturbance of signal waveform. This impedance matching must be done not only at the receiving end of the signal line but also at the transmitting end. This is necessary to absorb reflections from impedance un-matched points, such as a connector and a package, at the transmitting end as well.
Among known methods practiced to reduce the number of signal lines are bidirectional transmission and multilevel transmission that transmit a plurality of bits using one symbol, but these methods require not only that the value of line termination be matched to the line impedance, but also that its nonlinearity be minimized. This is because if nonlinearity exists, in bidirectional transmission an error would occur when subtracting from the received signal the contribution being made by the driver at the receiving end, while in the case of multilevel transmission, the number of bits per symbol would be limited.
The prior art and problems associated with the prior art will be described in detail later with reference to drawings.
An object of the present invention is to provide a receiver and hybrid circuit for bidirectional signal transmission, that resolve the problem of the kick-back noise that a hybrid circuit has on its input side. Another object of the invention is to achieve bidirectional transmission or multilevel transmission capable of utilizing the bandwidth of transmission line efficiently by providing linearity to the impedance of a driver circuit.
According to the present invention, there is provided a receiver for bidirectional signal transmission in which signals are sent and received in both directions over a signal transmission line, comprising a signal line connected to the signal transmission line; a first hold capacitor for holding a signal; a signal line voltage buffer circuit for buffering a voltage of the signal line; a hybrid circuit for outputting a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit; and a decision circuit for making a decision on the logic value of the received signal separated and output by the hybrid circuit.
The decision circuit may generate a sum of a signal value obtained at the time that the hybrid circuit makes a decision on the logic value of the received signal separated and output by the hybrid circuit and a value obtained by multiplying an earlier obtained given signal value by a coefficient, and makes the decision by using the value of the generated sum. The buffer circuit may be a voltage buffer circuit, and the hybrid circuit may be a capacitive coupling hybrid circuit. The voltage buffer circuit may have a voltage gain of nearly unity, and the voltage buffer circuit and the signal line may be coupled together by a capacitor, and wherein during a non-operating period of the voltage buffer circuit, a node on the input side of the capacitor may be connected to an output of the voltage buffer circuit and an input node of the voltage buffer circuit may be precharged to a prescribed potential, thereby compensating for an offset voltage of the voltage buffer circuit.
The receiver may further comprise a reference voltage output circuit for controlling, in accordance with an output sequence of a driver a reference voltage for driving, an input node of the capacitive coupling hybrid circuit. The reference voltage output circuit may comprise a control voltage generating circuit for generating a plurality of control voltages in accordance with data of a signal sequence being sent out by the driver; a plurality of reference voltage buffers for receiving the control voltages and for generating respective reference voltages; and a selection circuit for selecting an output of one of the plurality of reference voltage buffers in accordance with the data of the signal sequence.
The buffer circuit may be a transconductor for performing voltage-to-current conversion; and the hybrid circuit may convert the voltage of the signal line and a signal voltage of a replica driver into currents by using the transconductor, and may cause a current corresponding to the difference between the converted currents to flow into a load device to obtain the difference between the voltage of the signal line and the signal voltage of the replica driver, thereby separating the received signal for output. An offset compensating circuit including a first transistor and a second hold capacitor may be connected to the load device to which the current from the transconductor is supplied in the hybrid circuit; and in the offset compensating circuit, during a non-operating period of the buffer circuit, the first transistor may be connected in a diode-connected configuration and the second hold capacitor may be connected to a gate of the first transistor, while during an operating period of the buffer circuit, voltage on the second hold capacitor holds the gate voltage of the first transistor.
The current from the transconductor may be held using a hold circuit of a folded structure having a third hold capacitor and a second transistor, and wherein during a sampling period, the third hold capacitor may be connected to a gate of the second transistor connected in a diode-connected configuration and, during a holding period, the third hold capacitor may be disconnected from the gate and an output current from the hold circuit may be coupled to a load device that follows the hold circuit, thereby generating a weighted sum of signals taken at two adjacent sampling instants and thereafter making the decision using the weighted sum. The buffer circuit may include at an output stage thereof a push-pull source follower stage comprising an nMOS device and a pMOS device.
Further, according to the present invention, there is provided a receiver for bidirectional signal transmission in which signals are sent and received in both directions over a signal transmission line, comprising a signal line connected to the signal transmission line; a first hold capacitor for holding a signal; a hybrid circuit for outputting a received signal by separating the received signal from a voltage of the signal line; a reference voltage output circuit for outputting in accordance with an output sequence of a driver a reference voltage for driving an input node of the hybrid circuit; and a decision circuit for making a decision on the logic value of the received signal separated and output by the hybrid circuit.
The reference voltage output circuit may comprise a control voltage generating circuit for generating a plurality of control voltages in accordance with data of a signal sequence being sent out by the driver; a plurality of reference voltage buffers for receiving the control voltages and for generating respective reference voltages; and a selection circuit for selecting an output of one of the plurality of reference voltage buffers in accordance with the data of the signal sequence.
Further, according to the present invention, there is also provided a hybrid circuit for bidirectional signal transmission in which signals are sent and received in both directions over a signal transmission line, wherein the hybrid circuit is a capacitive coupling hybrid circuit having a hold capacitor for holding a signal, and wherein an input signal from the signal transmission line is supplied to the hold capacitor via a buffer circuit, and a received signal is output by separating the received signal from a signal line voltage buffered by the buffer circuit.
The hybrid circuit may further comprise a reference voltage output circuit for outputting in accordance with an output sequence of a driver a reference voltage for driving an input node of the capacitive coupling hybrid circuit. The reference voltage output circuit may comprise a control voltage generating circuit for generating a plurality of control voltages in accordance with data of a signal sequence being sent out by the driver; a plurality of reference voltage buffers for receiving the control voltages and for generating respective reference voltages; and a selection circuit for selecting an output of one of the plurality of reference voltage buffers in accordance with the data of the signal sequence.
The hybrid circuit may receive an output signal of a replica driver, which outputs a signal corresponding to an output of a driver that amplifies a signal and outputs the amplified signal onto the signal transmission line, an input signal from the signal transmission line, and a reference voltage, and separates the received signal for output. The hybrid circuit may convert the voltage of the signal transmission line and the output voltage of the replica driver into currents by using a transconductor, and may cause a current corresponding to the difference between the converted currents to flow into a load device to obtain the difference between the voltage of the signal transmission line and the output voltage of the replica driver, thereby separating the received signal for output. An offset compensating circuit may comprise a first transistor and a first hold capacitor may be connected to the load device to which the current from the transconductor is supplied in the hybrid circuit; and in the offset compensating circuit, during a non-operating period of the buffer circuit, the first transistor may be connected in a diode-connected configuration and the first hold capacitor may be connected to a gate of the first transistor, while during an operating period of the buffer circuit, voltage on the first hold capacitor holds the gate voltage of the first transistor.
The current from the transconductor may be held using a hold circuit of a folded structure having a second hold capacitor and a second transistor, and wherein, during a sampling period, the second hold capacitor may be connected to a gate of the second transistor connected in a diode-connected configuration, and during a holding period, the second hold capacitor may be disconnected from the gate and an output current from the hold circuit may be coupled to a load device that follows the hold circuit, thereby generating a weighted sum of signals taken at two adjacent sampling instants and thereafter making the decision using the weighted sum.
According to the present invention, there is also provided a driver circuit comprising a first transistor having a first terminal connected to an output signal line, a second terminal connected to a first power supply line, and a control terminal; a second transistor connected in parallel with the first transistor and having a first terminal, a second terminal, and a control terminal; and a control circuit for controlling a voltage to be applied to the control terminal of the second transistor, in accordance with a potential of the output signal line.
The first power supply line may be a high voltage supply line, and the first transistor may operate to pull up the output signal line. The first power supply line may be a low voltage supply line, and the first transistor may operate to pull down the output signal line. The control circuit may be a voltage shift circuit which produces a shift voltage by shifting the voltage of the output signal line by a given value in an approximating manner, and which applies the shift voltage to the control terminal of the second transistor. The voltage shift circuit may produce the shift voltage by flowing current through a voltage shifting load device connected to the output signal line. The voltage shifting load device and the first and second transistors may be of the same channel conductivity type. The driver circuit may further comprise an injecting circuit for injecting a charge or current for speeding up an OFF to ON change of the voltage applied to the control terminal of the second transistor when switching the second transistor from an OFF state to an ON state.
Further, according to the present invention, there is provided a diver circuit comprising a first transistor having a first terminal connected to an output signal line, a second terminal connected to a high voltage supply line, and a control terminal, the first transistor operating to pull up the output signal line; a second transistor connected in parallel with the first transistor and having a first terminal, a second terminal, and a control terminal; a first control circuit for controlling a voltage to be applied to the control terminal of the second transistor, in accordance with a potential of the output signal line; a third transistor having a first terminal connected to the output signal line, a second terminal connected to a low voltage supply line, and a control terminal, the third transistor operating to pull down the output signal line; a fourth transistor connected in parallel with the second transistor and having a first terminal, a second terminal, and a control terminal; and a second control circuit for controlling a voltage to be applied to the control terminal of the fourth transistor, in accordance with the potential of the output signal line.
The driver circuit may be a differential constant-current driver, and the paralleled first and second transistors and the paralleled third and fourth transistors may act loads for the differential constant-current driver. The first control circuit may be a first shift voltage circuit which produces a first shift voltage by shifting the voltage of the output signal line of the driver by a given value in an approximating manner, and which applies the first shift voltage to the control terminal of the second transistor, and the second control circuit may be a second shift voltage circuit which produces a second shift voltage by shifting the voltage of the output signal line of the driver by a given value in an approximating manner, and which applies the second shift voltage to the control terminal of the fourth transistor. The first and second voltage shift circuits may produce the first and second shift voltages, respectively, by flowing current through voltage shifting load devices connected to the output signal line. The voltage shifting load devices and the first to fourth transistors may be of the same channel conductivity type.
The driver circuit may further comprise a first switch circuit inserted between the first control circuit and the control terminal of the second transistor, and a second switch circuit inserted between the second control circuit and the control terminal of the fourth transistor, and wherein, when either a pull-up load device constructed from the first and second transistors or a pull-down load device constructed from the third and fourth transistors is turned ON, a corresponding one of the first and second switch circuits may be turned ON and the other switch circuit may be turned OFF. The driver circuit may further comprise a pull-up circuit for pulling up the control terminal of the second transistor, and a pull-down circuit for pulling down the control terminal of the fourth transistor, and wherein, when the first switch circuit is turned OFF, the pull-up circuit may pull up the control terminal of the second transistor, and when the second switch circuit is turned OFF, the pull-down circuit may pull down the control terminal of the fourth transistor.
In addition, according to the present invention, there is provided a driver circuit comprising a first transistor having a first terminal connected to an output signal line, a second terminal connected to a first power supply line, and a control terminal; and a control circuit for controlling a voltage to be applied to the control terminal of the first transistor, in accordance with a control signal and a potential of the output signal line.
The first power supply line may be a high voltage supply line, and the first transistor may operate to pull up the output signal line. The first power supply line may be a low voltage supply line, and the first transistor may operate to pull down the output signal line. The control circuit may comprise a resistive device for connecting between the output signal line and the control terminal of the first transistor, and a resistive device control circuit for controlling the resistance of the resistive device by a voltage.
The control circuit may be a circuit constructed by combining a resistive device and a switch device. The switch device may be a transistor or a diode, and the control circuit may produce an output voltage whose dependence on the control signal and the potential of the output signal line is obtained by a so-called polygonal approximation circuit. The control circuit may include a capacitor for connecting between the output signal line and the control terminal of the first transistor. The control circuit may include a diode-connected transistor for connecting between the output signal line and the control terminal of the first transistor. A device for connecting between the output signal line and the control terminal of the first transistor may be of the same conductivity type as the first transistor, and a circuit for applying a bias current to the control circuit may be controlled so as to provide an impedance scaled to the impedance level of the first transistor.
According to the present invention, there is also provided a diver circuit comprising a first transistor having a first terminal connected to an output signal line, a second terminal connected to a high voltage supply line, and a control terminal, the first transistor operating to pull up the output signal line; a first control circuit for controlling a voltage to be applied to the control terminal of the first transistor, in accordance with a first control voltage and a potential of the output signal line; a second transistor having a first terminal connected to the output signal line, a second terminal connected to a low voltage supply line, and a control terminal, the second transistor operating to pull down the output signal line; and a second control circuit for controlling a voltage to be applied to the control terminal of the second transistor, in accordance with a second control signal and the potential of the output signal line.
The first and second control circuits may each comprise a resistive device for connecting between the output signal line and the control terminal of a corresponding one of the first and second transistors, and a resistive device control circuit for controlling the resistance of the resistive device by a voltage. The first and second control circuits may be each constructed by combining a resistive device and a switch device. The switch device may be a transistor or a diode, and the first and second control circuits may each produce an output voltage whose dependence on the first or second control signal and the potential of the output signal line is obtained by a so-called polygonal approximation circuit.
The first and second control circuits may each include a capacitor for connecting between the output signal line and the control terminal of the first transistor. The first and second control circuits may each include a diode-connected transistor for connecting between the output signal line and the control terminal of a corresponding one of the first and second transistors. A device for connecting between the output signal line and the control terminal of a corresponding one of the first and second transistors may be of the same conductivity type as the first and second transistors, and a circuit for applying a bias current to the first and second control circuits may be controlled so as to provide an impedance scaled to the impedance level of the first and second transistors.
In addition, according to the present invention, there is also provided a signal transmission system having a first driver circuit, a second driver circuit, and a signal transmission line; the first driver circuit and the second driver circuit being coupled through the signal transmission line, and bidirectional signal transmission being performed with each driver acting as a receiving end of a signal transmitted from the other through the signal transmission line, wherein each of the first and second driver circuit comprises the above described features.